1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A reduction in the size of a semiconductor element enables not only an integration of even more circuits per unit area, but also enables a drive of the semiconductor element at a lower voltage and at a lower current to suppress the power consumption. The reduction in the size of the semiconductor element, however, brings about a shift in the device characteristics from the long channel approximation. Specifically, the shift includes a fluctuation of the threshold voltage, a lowering of the source and drain withstand voltage, and an increase of the source-to-drain leakage current in a weak inversion state. These phenomena are generally called short channel effect. An LDD (lightly-doped-drain) structure is known as a scheme for preventing the short channel effect. The LDD structure is a structure in which a low impurity concentration region intervenes between high impurity concentration drain and source regions and channel region. Employment of the LDD structure weakens the electric field in the vicinity of the ends of the drain and the source, to improve the withstand voltage thereof.
Patent Document 1 (Japanese Laid-Open Patent Publication No. 10-12870) describes a semiconductor device and a fabrication method of the same, the semiconductor device having a low-concentration impurity layer and a high-concentration impurity layer that are disposed overlapping with a gate electrode between the high impurity concentration drain and source regions and channel region.